What is the biggest conceptual culture shock when transitioning from Modbus/DNP3 to DLMS/COSEM?

[elena_rostova]

️ Technical Redaction & Safe Harbor Warning:
Industrial register maps and proprietary meter firmware architectures have been generalized.

After 5 years developing Modbus RTU firmware where reading a value was as simple as function code 0x03 on register 40001, transitioning to DLMS / COSEM (IEC 62056-62 Clause 3.2) to read voltage 1.0.32.7.0.255 feels like a massive conceptual leap:

• First, SNRM/UA handshake on HDLC layer;
• Then, AARQ association with ACSE mechanism names and conformance blocks;
• Then, A-XDR nested structures, scalers, unit enums, and Class 3/4 register models;
• Finally, AES-GCM encryption with Invocation Counters.

For embedded developers moving from flat industrial protocols to DLMS, what was the most surprising design philosophy difference?

[alex_turner]

The fundamental divergence lies in PLC memory address mapping vs Legal Metrology Object Contracts:

• Modbus (Process Control Philosophy):
  A register like 40001 is purely raw bytes in PLC SRAM. The protocol does not know if it represents Celsius, Volts, or RPM. It relies entirely on external static Excel mapping sheets. There is zero security, zero timestamping, and zero non-repudiation.

• DLMS / COSEM (Self-Describing Legal Metrology Philosophy):
  Every metering value is an object instance per IEC 62056-62. A Class 3 Register (1.0.1.8.0.255) contains its value, signed scaler exponent, engineering unit enum (30 = Wh), and access permissions. Any standard client worldwide can discover and interpret the data without a manufacturer manual.

When managing 20 million meters from 15 different vendors in a national smart grid, DLMS object standardization saves millions in integration costs.

[david_miller]

On the other hand, the embedded footprint cost is substantial:
A Modbus slave needs 200 lines of C and 512 bytes of RAM.
A compliant DLMS stack with COSEM object dictionary, A-XDR dynamic decoder, HDLC segmentation buffers, and AES-GCM cryptography requires at least 32KB RAM and 128KB Flash per Blue Book Section 4.4, driving the industry transition from 8-bit MCUs to ARM Cortex-M0+/M4.

[elena_rostova]

Looking closely at @alex_turner's explanation of self-describing legal contracts, the complexity makes sense now.
Reading a scaled register value for 1.0.1.8.0.255:

02 02 06 00 00 03 E8 12 00 1E

decodes to a structure containing integer 1000, scaler 0, and unit 30 (Wh). The overhead delivers interoperability per IEC 62056-62.